Inhibit pulse driver



y 7, 1964 D. SHANSKY ETAL 3,140,400

INHIBIT PULSE DRIVER Filed July 22, 1959 JII INFO T GONTP j INVENTORS DA V/D SHANSK Y WALTER STRUHME/ER A TTOR/VEY United States Patent O 3,140,400 INHIBIT PULSE DRIVER David Shansky, South Lincoln, and Walter Strohmeier,

Newton Highlands, Mass., assignors to Minneapolis- Honeywell Regulator Company, Minneapolis, Minn., a

corporation of Delaware Filed July 22, 1959, Ser. No. 828,742 7 Claims. (Cl. 307-88) A general object of the present invention is to provide a new and improved electrical pulse producing circuit. More specifically, the present invention is concerned with a new and improved electrical apparatus for providing an electrical control pulse for a coincident current type memory wherein the circuitry is characterized by its simplicity, its high speed of operation, and its ability to produce a signal of uniform dimension.

A Well-known form of digital storage circuit or memory is known as a coincident current memory. Such a memory generally incorporates a plurality of ferrite cores which are adapted to be arranged in a predetermined array. A plurality of selection wires thread the cores of the array so that a pair of control wires or windings pass through each core. The wires are selectively addressable so that it is possible to change the electrical state of any one core in the array for digital storage purposes. When it is desired to read information out of a core, an application of the proper selection signals of proper polarity to the wires leading through the core will cause a switching of the core to produce an output signal which may be utilized by some external circuitry. A representative form of a coincident current storage array of the type in which the present invention may be useful is illustrated in the Forester Patent Number 2,736,880, issued February 28, 1956.

Inasmuch as it is generally desired to control the writing of information into a selected core, it is possible to effect this control by a third winding passing through the core and applying thereto an inhibit signal which serves to cancel out the effects of a select signal applied to one of the selection lines. In this type of circuitry, the magnitudes of the electrical pulses must be closely regulated in order to be certain that the cores in the array are not inadvertently switched due to the fact that a signal on one of the select lines is large enough to switch a core independently of the action of any of the other lines. It is important that it not only produce regulated pulses for the select lines, but also regulated lines for the inhibit line associated with the cores.

The present invention defined in the specification makes it possible to produce a very closely regulated control pulse for a memory plane wherein a control pulse is produced by a circuit means having a very high switching rate which makes it usable with very high-speed memory circuits.

It is therefore a more specific object of the invention to provide a new and improved apparatus for producing a regulated inhibit pulse for use in switching a memory line.

The objects of the invention are achieved by the use of a magnetic core device which is adapted to be switched into a predetermined electrical state upon the appearance of an input information signal. The magnetic core device will switch to such a state at a very high rate for the reason that the core, during this initial switching operation, is not loaded. When it is desired to switch the core to produce a controlled output pulse, the input control winding to the core is de-energized and a direct current bias connected to a winding on the core serves to switch the core back to its initial state to produce an output pulse.

The control signals applied to the pulse-producing formation source. receive a positive signal, which serves as a control sig- 3,140,400 Patented July 7,1964

core are derived from a transistor switching circuit which is adapted to store internally an applied information signal and respond quickly to the control signal in the event that it is desired to change the conducting state of the transistor.

It is therefore a still further more specific object of the present invention to provide a new and improved pulse-producing circuit for a memory plane wherein an electronic switch having internal storage properties is connected to control current flowing in a control winding of a magnetic core, and wherein the electronic switch is adapted to be quickly changed into a non-conducting state when it is desired that the associated core device produce an output signal.

The foregoing objects and features of novelty which characterize the invention, as well as other objects of the invention, are pointed out with particularity in the claims annexed to and forming a part of the present specification. For a better understanding of the invention, its advantages and specific objects attained with its use, reference should be had to the accompanying drawings and descriptive matter in which there is illustrated and described a preferred embodiment of the invention.

Of the drawings:

FIGURE 1 is a schematic representation of a preferred form of the invention; and

FIGURE 2 illustrates a typical wave form that may be associated with apparatus of the type shown in FIG- URE 1.

Referring first to FIGURE 1, the numeral 10 identifies a memory plane which may be a coincident current memory plane of the type described in the abovementioned Forester patent. This memory plane may be adapted to have input selection X and Y wires to which appropriate address selection signals may be applied. An

inhibit line designated as a Z line is also provided for the memory plane 10 and is adapted to receive a control signal from the circuitry of the present invention. The memory plane may further have a series of output lines S for sensing the signals derived when a particular selection is made within the plane 10.

The source of electrical pulse signals for the Z line or the inhibit line in plane 10 is a ferrite core 12, having a rectangular hysteresis characteristic. The ferrite core 12 has an input control winding 14, a reset winding 16, and an output winding 18. The winding 18 is coupled to the Z line by way of a diode 20, which serves to pass only those signals from the output winding which are associated with the resetting of the core.

' electrodes.

Connected to the base of the transistor 28 are a pair of input terminals 30 and 32. The terminal 30 is connected by way of a diode 34 to the base, while the terminal 32 is connected to the base by way of a resistor The input terminal 30 is adapted to receive a negative input signal representing information derived either from the memory during a readout, or from some external in- The input terminal 32 is adapted to f nal, for initiating the cutoff of the transistor 28 if it had previously been turned on by an information signal.

Referring to FIGURE 2, in considering the operation of the system, the normal memory plane is adapted to be cycled through a reading operation and then a writing a operation. During the reading operation a pair of halfselect signals are applied to a selected X and Y wire in the array to a single core in the manner described in the aforementioned Forester patent. The X and Y pulses are assumed, in FIGURE 2, to be positive pulses. The adding of the half-select signals from the X and Y wires will produce a full select signal on a particular core in the plane, and will cause the core to switch to a first of its two stable states. Upon the subsequent application of write signals or negative signals to the corresponding X and Y wires in the memory, the core will be switched to its opposite stable state. In the event that it is desired to inhibit the switching of the core back to its initial state, the application of a Z pulse, or inhibit pulse, will serve to cancel out the effect of one of the select signals so that only a half-select current will remain on the core, and the core will not be switched.

Inasmuch as the memory plane requires closely regulated pulses, the present invention has been designed to provide such pulses with a minimum of circuitry producing an optimum type of pulse. The manner in which the pulse for the Z line is produced will be readily apparent when it is noticed that a pulse applied to the input terminal 30 will be passed by way of the diode 34 to the base of the transistor 28. This pulse may be derived from an external source or it may be read out of the memory through the sense line S to be re-introduced by way of the input terminal 30 in order to retain the data which was read out. The application of the pulse will switch the transistor 28 into the conducting state, and the ferrite core 12 will be switched into a set state. The current-turns ratio of the winding 14 is selected so that it will overcome the fixed current-turns ratio of the winding 16. The switching of the core 12 into the set state will be eifected very rapidly for the reason that there will be no loading of the core. Since the output winding 18 has the diode 20 in series therewith, the diode 20 acts as a high impedance to the output pulse resulting from the switching of the core 12. to the set state.

When the information pulse applied to the base of the transistor 28' disappears, the hole storage within the transistor will serve to maintain the transistor 28 in the conducting state, and this will hold the core 12 in the set state. At the instant that it is desired to cause the transistor 28 to be rendered non-conducting, a control pulse is applied by way of the input terminal 32 to bias the transistor to be non-conducting. With the current flow through the winding 14 stopped, the direct current bias acting through the resistor 24 and winding 16 on the core 12 serves to reset the core. When the current flowing through the winding 16 resets the core 12, there will be produced in the output winding 18 a control pulse which will pass through the diode 20 and into the inhibit line Z. This will serve to inhibit the etfects of the selection signals on the X and Y lines.

In the event that there is no information to be written into the memory plane at the address selected by the X and Y wires, there will be no information pulse applied to the input 30 and, consequently, the transistor 28 will remain non-conducting. Thus, the core 12 will remain in a reset state and there will be no output signal tending to inhibit the selection signals from the X and Y wires of the memory. In this case, the read selection signals will switch the cores in the memory plane to a first state and then the write signals appearing upon the same selection wires will switch the core back into the original state.

While, in accordance with the provisions of the statutes, there has been illustrated and described the best form of the invention known, it will be apparent to those skilled in the art that changes may be made in the apparatus described without departing from the spirit of the invention as set forth in the appended claims, and that in some cases, certain features of the invention may be used to advantage without a corresponding use of other features.

Having now described the invention, what is claimed as i new and novel and for which it is desired to secure Letters Patent is:

1. An inhibit driver for a core memory plane comprising a data input terminal, a transistor having first, second and third terminals, a magnetic core having an input set winding, a reset winding conductively isolated from said set winding, and an output winding, means connecting said second and third transistor terminals to control the current flowing in said set winding, means connecting said data input terminal to said first transistor terminal, means for selectively applying information and cut-off signals respectively to said input terminal, means connecting a direct current biasing source to said reset winding, and means for deriving output pulses from said output winding.

2. An inhibit driver for a core memory plane comprising a data input terminal, a transistor having first, second and third terminals, a magnetic corehaving an input set winding, a reset winding conductively isolated from said set winding, and an output winding, means connecting said second and third transistor terminals to control the current flowing in said set winding, means connecting said data input terminal to said first transistor terminal to switch said transistor into a conductive state when a data pulse is present, means for selectively applying a cut-off pulse to said input terminal to render said transistor nonconductive, means connecting a direct current biasing source to said reset winding to reset said core when said transistor is non-conductive, and means for deriving inhioit pulses from said output winding.

3. An inhibit driver for a core memory plane comprising a data input terminal, a transistor having first, second and third terminals, a magnetic core having an input set winding, a reset winding conductively isolated from said set winding, and an output winding, means connecting said second and third transistor terminals to control the current flowing in said set winding, means connecting said data input terminal to said first transistor terminal, means for selectively applying information and cut-off signals respectively to said input terminal, means connecting a direct current biasing source to said reset winding, and diode means connected to said output winding to derive inhibit pulses therefrom, said diode means being poled to block the output signal in said output winding when said core is being set.

4. Apparatus for producing an inhibit pulse for a memory plane comprising a bistable magnetic core having a set winding, a reset winding conductively isolated from said set winding, and an output winding, an electronic switch connected in series with said input winding and being adapted, when actuated, to switch said core to a set state, means for selectively deactivating said electronic switch, a direct current source connected to said reset winding to switch said core to a reset state when said electronic switch is not actuated, said memory plane including an inhibit winding, and means connecting said output winding to said inhibit winding.

5. Apparatus for producing an inhibit pulse for a memory plane comprising a bistable magnetic core having a set winding, a reset winding conductively isolated from said set winding, and an output winding, a transistor switch having internal signal storage properties connected in series with said input winding and being adapted, when conducting, to switch said core to a set state, a signal input source connected to said transistor switch to render said switch non-conductive, a direct current source connected to said reset winding to switch said core to a reset state when said electronic switch is not actuated, said memory plane including an inhibit winding, and means connecting said output Winding to said inhibit winding.

6. Apparatus for producing an inhibit pulse for a memory plane comprising a bistable magnetic core having a set winding, a reset winding conductively isolated from said set winding, and an output winding, an electronic switch having internal signal delay properties connected in series with said input winding and being adapted, when actuated, to switch said core to a set state, a direct current source connected to said reset winding to switch said core to a reset state when said electronic wit h i 2,734,184 Rai hm n Feb. 7, not actuated, said memory plane including an inhibit 5 2,760,088 Rlttman 6t Aug. 21, winding, and diode means coupling said output wi din 2,825,320 $11118 Mar. 4, to said inhibit winding when said core is switched to said 2,910,594 Bauer et l- Oct. 27, reset state. 2,953,741 Pittman et a1 Sept. 20,

7. Apparatus as defined in claim 6 wherein th ur t- 2,959,686 Gutterman Nov. 8, 1960 turns ratio of said set winding exceeds the current-turns 10 ratio of said reset winding.

References Cited in the file of this patent UNITED STATES PATENTS 

6. APPARATUS FOR PRODUCING AN INHIBIT PULSE FOR A MEMORY PLANE COMPRISING A BISTABLE MAGNETIC CORE HAVING A SET WINDING, A RESET WINDING CONDUCTIVELY ISOLATED FROM SAID SET WINDING, AND AN OUTPUT WINDING, AN ELECTRONIC SWITCH HAVING INTERNAL SIGNAL DELAY PROPERTIES CONNECTED IN SERIES WITH SAID INPUT WINDING AND BEING ADAPTED, WHEN ACTUATED, TO SWITCH SAID CORE TO A SET STATE, A DIRECT CURRENT SOURCE CONNECTED TO SAID RESET WINDING TO SWITCH SAID CORE TO A RESET STATE WHEN SAID ELECTRONIC SWITCH IS NOT ACTUATED, SAID MEMORY PLANE INCLUDING AN INHIBIT WINDING, AND DIODE MEANS COUPLING SAID OUTPUT WINDING TO SAID INHIBIT WINDING WHEN SAID CORE IS SWITCHED TO SAID RESET STATE. 